Avalanche Photodiodes (APDs) are photodetectors that use avalanche multiplication to achieve internal gain. Many prior art sources describe photodetectors, such as J. C. Campbell, “Recent Advances in Telecommunications Avalanche Photodiodes,” J. Lightwave Technology v. 25(1) Pp. 109-121 (2007), which are hereby incorporated by reference. Single photon avalanche photodiodes (SPADs) are a specific class of avalanche photodiodes that are capable of detecting single photons. Examples of SPADs are given for example in S. Cova, et al. “Evolution and prospects for single-photon avalanche diodes and quenching circuits,” J. Modern Optics v. 51(9-10) Pp. 1267-1288 (2004), which is hereby incorporated by reference.
APD and SPAD arrays are also known in the art, and include a range of devices such as the silicon photomultiplier (SiPM), the multi-pixel photon detector (MPPC), and a number of similar devices. Reference is made to the digital SiPM (dSiPM) approach disclosed in US Pub. Nos. 2011/0079727, 2010/0127314, and T. Frach et al. “The Digital Silicon Photomultiplier—System Architecture and Performance Evaluation,” 2010 IEEE Nuclear Science Symposium Conference Record (NSS/MIC), Pp. 1722-1727 (2010), which are hereby incorporated by reference. Other examples of prior devices are described in International Workshop on New Photon-detectors 2012, LAL Orsay, France, and the presentation entitled “The SiPM Physics and Technology—a Review—,” G. Collazuol, found online at the time of this submission at http://indico.cern.ch/getFile.py/access?contribId=72&resId=0&materialld=slides&c onfld=164917; W-S Sul et al. “Guard Ring Structures for Silicon Photomultipliers,” IEEE Electron; Dev., Lett, v. 31(1) Pp 41-43 (2010); A. G. Stewart et al. “Performance of 1-mm2 Silicon Photomultiplier,” IEEE J. Quantum Electronics Vol. 44(2) pp. 157-164, (2008), all of which are hereby incorporated by reference. A simple SPAD array devices incorporates a single photon avalanche diode (SPAD) and a passive quench circuit. The passive quench circuit consists of a current limiting element (usually a resistor) in parallel with a bypass capacitor as described in S. Tiza et al. “Electronics for single photon avalanche diode arrays,” Sensors and Actuators A 140, Pp. 113-122 (2007) and S. Seifert et al. “Simulation of Silicon Photomultiplier Signals,” IEEE Trans. Nuclear Science, v. 56(6) Pp. 3726-3733 (December 2009). All of the above references are incorporated herein by references.
Prior art APD arrays have also used various techniques for isolating adjacent APD elements. For example PN junction isolation and mesa isolation are well known in the prior art. PN junction isolation is generally achieved by confining the lateral extent of doping to separate p-type regions (on an n-type substrate) or n-type regions (on a p-type substrate) or both. Edge effects in isolated devices often results in electrical field crowding along the perimeter of the APD device, which would normally cause a non-uniform avalanche gain profile. Edge effects in isolated devices are mitigated through the use of double-diffused structures, guard ring structures, or other approaches well known in the state of the art (see, for example, Y. Liu, S. R. Forrest, J. Hladky, M. J. Lange, G. H. Olsen, and D. E. Ackley, “A Planar InP/InGaAs Avalanche Photodiode with Floating Guard Ring and Double Diffused Junction,” J. Lightwave Technology, v. 10(2) February 2991, and Chapter 3: Breakdown Voltage in Power Semiconductor Devices, Pp. 67-127 by B. J. Baliga, PWS Publishing Company, Boston, Mass. 1996).
Mesa isolation can be used to define the active area of a APD and to laterally isolate adjacent APD elements, by partially or fully removing the conductive pathway between adjacent APD elements. The use of a beveled edge structure in mesa isolation can be used to mitigate edge effects, but places stringent demands on the mesa structure (bevel angle) and surface state density of the mesa. Beveled edge mesa structures are described in detail by B. J. Baliga “Power Semiconductor Devices,” Pp. 103-111, PWS Publishing Company, Boston, Mass., which is hereby incorporated by reference.
Ion implantation isolation is used to render a semiconductor region insulating, semi-insulating, or very low conductivity. Ion implantation isolation is often used with respect to compound semiconductor devices where ion implantation creates a sufficient amount of deep levels in a semiconductor region to compensate some the doping in said semiconductor region, thereby reducing conductivity and often rendering the region highly resistive. For all cases of ion implantation isolation, a residual conductivity remains, with experimental values exceeding 1E9 ohms/square, though somewhat lower values of resistivity are common. The residual conductivity is often attributed to residual free carrier conductivity and/or hopping conduction. For compound semiconductors such as GaAs, AlGaAs, GaInP, InGaAsP, and InAlInN, implant isolation is often achieved by using hydrogen ions, helium ions, oxygen ions, nitrogen ions, boron ions, fluorine ions, arsenic ions, and phosphorous ions, through those skilled in the art will recognize that any suitable ion may be used. The residual conductivity is a function of the implant species, implant energy, implant dose, and implant profile. While conventional ion implantation for doping generally achieves (at most) 1 free carrier for each dopant atom, ion implantation isolation achieves a multiplier effect whereby implantation of a single atom (or species) can produce a 10-fold or higher reduction in the free carrier concentration. This occurs because the lattice damage induced by the implanted ion produces the compensating donors/acceptors, and not the specific ion itself. In some cases, the specific ion may also be used as a compensating level, such as through the use of arsenic implantation in GaAs. Ion implant isolation is well known in the literature, as illustrated by one or more of the following references: Q. Zhou, et al. “Proton-Implantation-Isolated 4H—SiC Avalanche Photodiodes,” IEEE Photonics Technology Lett. v. 21(23) Pp. 1734-1736 (2009); I. Sandall, et al. “Planar InAs photodiodes fabricated using He ion implantation,” Optics Express v. 20(8) Pp. 8575-8583 (2012); Q. Zhou, et al. “Proton-Implantation-Isolated Separate Absorption Charge and Multiplication 4H—SiC Avalanche Photodiodes,” IEEE Photonics Technology Letters v. 23(5) Pp. 299-301 (2011); G. E. Bulman, et al. “Proton isolated In0.2Ga0.8As/GaAs strained layer superlattice avalanche photodiode,” Appl. Phys. Lett. v. 48, Pp. 1015-1017 (1986); I. Danilov, et al. “Electrical isolation of InGaP by proton and helium ion irradiation,” J. Appl. Phys., v. 92 Pp. 4261-4265 (2002); S. J. Pearton, “Ion Implantation for Isolation of III-V Semiconductors,” Materials science reports, v. 4(8), (1990); Vasteras Willy Hermansson, et al. in U.S. Pat. No. 5,914,499, entitled “High Voltage Silicon Carbide Semiconductor device with bended edge” (1999); Tzu-Yu Wang, U.S. Pub. No. 2005/0078725, entitled “Methods for Angled Ion Implantation of Semiconductor Devices, (2005); and D. B. Slater, et al., U.S. Pat. No. 7,943,406 “LED Fabrication via ion implant isolation” (2011).
A physical beveled edge mesa structure can be fabricated on a photodetector as illustrated in FIG. 1. Semiconductor layers 101 and 102 are formed on a semiconductor substrate 100 using techniques known in the art. Layer 101 is an n-type semiconductor layer with a thickness 111. Layer 102 is a p-type semiconductor layer with a thickness 112. The doping density of n-type semiconductor layer 101 is higher than the doping density of p-type semiconductor layer 102, such that the thickness or width 133 of the depletion region on the p-type side of the junction is larger than the thickness or width 134 of the depletion region on the n-type side of the junction. The dashed line 122 represents the edge of the depletion region in the p-type side of the device, while dashed line 121 represents the edge of the depletion region on the n-type side of the device.
With the appropriate choices for the doping densities in layers 101 and 102, and the bevel angle 131, the total depletion layer thickness 132 in the center portion of the device can be made smaller than the total depletion layer thickness 135 at the perimeter of the device, with the net result that the electric field in the center of the device is larger than the electric field along the perimeter of the device, which therefore allows the device performance to be dominated by the bulk properties of the semiconductor in the center of the device, and reduces the dependence of the device performance on the perimeter.
A challenge remains to fabricate effective avalanche photodetector devices, which have favorable performance and scalability yet have favorable dimensional and manufacturing characteristics. This disclosure addresses and remedies these and other failings of the prior art physical mesa photodetectors and similar devices.